PPAC @ IEEE Cluster'2009

Workshop on Parallel Programming on Accelerator Clusters (PPAC)

held in conjunction with IEEE Cluster'2009

August 31, 2009, New Orleans, LA

Scope

Accelerator-based parallel architectures, heterogeneous multi-core processors, FPGAs and GPUs, are rapidly becoming mainstream components for cluster computing. While the potential of accelerators for addressing problems such as memory latency and bandwidth has long been recognized, accelerators present several challenges to programmers and cluster systems designers. Conventional parallel programming models and libraries, parallel algorithms, and system software need to be restructured and redesigned to exploit the architectural strengths of accelerators and mitigate their lack of efficient general-purpose computing capabilities. This full-day workshop aims at bringing together researchers from academia and industry to discuss the latest developments in parallel programming models, languages, tools, system software and application development for clusters based on accelerators. Topics of interest include, but are not limited to:

Programming models for accelerator-based custers, including systems using GPUs, heterogeneous multi-core processors and FPGAs.
Compiler and runtime support for accelerator-based clusters, including support for scheduling, communication, and memory management.
Operating systems and virtualization support for accelerator-based clusters.
Performance evaluation of accelerator-based clusters, in particular with relation to conventional homogeneous clusters.
Performance analysis, profiling and debugging tools.
Application studies on accelerator-based clusters.
Power and energy-efficiency studies of accelerator-based clusters.

Schedule and Submissions

Papers due:	June 26, 2009 (closed)
Author notification:	July 21, 2009
Final papers due:	July 31, 2009
PPAC workshop:	August 31, 2009

Submitted manuscripts should be formatted according to IEEE Cluster 2009 proceedings guidelines.

The maximum length is 8 pages.
Single-spaced
8.5x11-inch, two-column numbered pages in IEEE Xplore format
Format instructions are available at:
- IEEE Paper LaTeX Template (ZIP file)
- IEEE Paper Word Template (ZIP file)

Submissions must be in pdf format and should be uploaded to http://www.easychair.org/conferences/?conf=ppac09. (Note: an EasyChair account is required.)

Organizers

Dimitris Nikolopoulos	Virginia Tech
Cal Ribbens	Virginia Tech

Program Committee

Eduard Ayguade	Barcelona Supercomputing Center
Kevin Barker	Los Alamos National Laboratory
Filip Blagojevic	Lawrence Berkeley National Laboratory
Mike Heroux	Sandia National Laboratory
Sven Karlsson	Technical University of Denmark
Jakub Kurzak	University of Tennessee
Jeffrey Vetter	Oak Ridge National Laboratory